The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
Embedded memory blocks are important components in programmable devices. Embedded memory blocks allow for bulk data storage within the device without the need for time-consuming off-device memory accesses. As a result of their extensive use, memory blocks often consume a substantial part of programmable devices' silicon area and between 10 and 20% of core dynamic power consumption in the average design, and a much higher proportion in some designs. Current programmable devices' embedded memory blocks are synchronous and primarily consume power due to internal memory core operations activated by the clock.
Typical programmable devices include a large number of embedded memory units of one or more fixed sizes. Additionally, these embedded memory units can have fixed configurations, including input and output data widths and memory depths, or variable configurations, including variable input and output data widths and memory depths.
To provide flexibility for programmable device designs, many design software applications enable designers to specify logical memory blocks of arbitrary size, input and output data widths, and other aspects. The design software application translates the desired logical memory block into a configuration of one or more embedded memory blocks. This corresponding configuration of embedded memory blocks, referred to as a physical memory, includes the configuration of the data widths and input, output, address, and control connections of each of its embedded memory blocks such that the behavior of the physical memory is identical to that of the specified logical memory. The physical memory can also include logic functions, such as logic gates, multiplexers, and demultiplexers, as needed to emulate the behavior of a specified logical memory. The translation of logical memories into corresponding sets of one or more embedded memory blocks and optional associated logic functions is performed by a series of mapping steps.
Design software applications can enable physical memories, that is sets of one or more embedded memory blocks and optional associated logic functions, to implement a wide variety of designer specified logical memories. Additionally, other logic functions can be implemented as physical memories, including shift registers, counters, and buffers such as FIFOs and LIFOs. Alternatively, these other logic functions can be implemented without embedded memory blocks by using only the programmable logic resources of the programmable device.
Currently, designers must optimize logical and physical memories for reduced power consumption manually. This optimization process is time-consuming and the designer must have extensive power-optimization experience and detailed knowledge of the underlying architecture of the programmable device. Additionally, this manual optimization process can be error-prone and the designers must be careful not to violate timing, area, and other design constraints when optimizing logical and physical memories for reduced power consumption.
It is therefore desirable for design software applications to automatically optimize the mapping of logical memories to physical memories for reduced power consumption. It is further desirable for design software application to optimize logic functions for reduced power consumption using physical memories such as embedded memory blocks or programmable logic resources. It is also desirable that the design software applications automatically optimize logical memories and other logic function for reduced power consumption without violating timing, area, or other constraints of the design.